Layout - Advanced Technology Node

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Neuron IP is actively seeking an Analog Layout Engineer to be an integral part of our team, focusing on custom high-speed analog layout for applications in High Speed SerDes, Memory PHY, RF, AI/ML, HPC, and automotive. This role is for you if you are passionate about mask design of analog circuits and wish to grow your skills in high-speed serial connectivity layout and analog layout in general. 

The Role:  

In our rapidly expanding analog and mixed-signal R&D group, you'll learn to create high-quality layouts for high-speed analog circuits using the latest FinFET and GAA CMOS technologies in some of the most advanced foundries on the planet. You'll play a key role in implementing SerDes & PLL sub-blocks, collaborating closely across disciplines with digital & analog design teams, foundry liaisons, system architects, and applications engineers to achieve first-pass silicon success. Neuron IP offers a state-of-the-art, remote-first working environment where every role is key to our technical success.  

The Person:  

We are looking for someone with at least 4 years of focused, practical experience in analog IC layout, preferably in FinFET technologies (e.g. 16nm and below). You will have a desire for constant learning and growth, a zeal for technical excellence, and an adaptable, positive mindset.  Your communication skills will shine in meetings, presentations, and written documentation. You are comfortable learning new skills for your role and acquiring an understanding of adjacent roles (e.g. circuit design, design for test, CAD/EDA, etc.) and are flexible enough to work with colleagues situated in different time zones.  We value creative thinkers and detail-driven problem-solvers who take the initiative to do what needs to be done, and who are interested in growing their skills beyond their job description. 

The Future: 

Neuron IP is a company committed to training and growing your career on the job.  You will work with experts in the various fields of design and layout, and will be given the tools, training and exposure to quickly grow you into one such expert in the field of layout with a broad experience in analog layout, and a deep expertise in high-speed wireline communications layout.  

Responsibilities: 

• Block level placement design, floor planning, signal flow/pin location planning  
• Plan and implement Power distribution plans (power grids), block integration into macros, and top-level integration of IP blocks/chips 
• Block level layout (placement and routing) of high-performance analog and mixed-signal blocks 
• Develop or fine-tune layout methodology for new technologies 
• Interface and collaborate with designers to develop and implement optimal layout approaches based on design best-practices. 
• Interfacing with foundry or client to tape-out chips. 
• Other duties and responsibilities as necessary 

Requirements: 

• Bachelor’s degree in engineering with practical analog IC layout experience. 
• Strong communication and documentation skills 
• Minimum 4 years of experience in analog layout, preferably in high-speed analog circuits, strong post-internship candidates with 2 years of experience in advanced node layout will also be considered. 
• Experience in finFET or deep sub-micron technologies strongly preferred 
• Understanding of physical verification (DRC, DFM, LVS) using Calibre EDA tools or similar. 

Strong candidates will possess at least some of the following:  

• Bachelor’s degree in electrical, electronic, telecommunications or computer engineering preferred 
• Experience in the layout of various SerDes sub-circuits, including CTLE, DFE, FFE, DAC/ADC based transmitters and receivers, PLL, DLL, LDO, Phase Interpolators, voltage-controlled oscillators, voltage/current-mode drivers, and bandgap references 
• Experience in layout of memory register components or similar 
• Experience directly leading chip or IP level integration or delivery 
• Working knowledge and understanding of transistor-level circuit design and CMOS/FinFET fabrication processes 
• Strong understanding of layout related trade-offs and their impact on performance (i.e. matching, symmetry, isolation, shielding, LDEs, etc.) 
• Experience with high-speed custom digital blocks (e.g. Serializer/De-serializer) 
• Understanding of ESD challenges in layout 
• Experience in coordinating tapeouts to a foundry and/or handoff of IP to digital integration teams 
• Knowledge of reliability design (EM, IR, aging) and layout considerations 
• Familiarity with Cadence, Synopsys EDA tools (Custom Compiler, Virtuoso or similar) 
• Familiarity with EDA scripting languages like SKILL, TCL, Perl, Python 

Neuron IP is a leader in Silicon IP, integrating advanced capabilities into SoCs efficiently. We're driving innovation in areas such as AI, the cloud, chiplets, 5G, and IoT. If you're passionate about pioneering technology, Neuron IP is your platform to excel.